An efficient and enhanced memory based FFT processor using radix 16 booth with carry skip adder

Abstract

The main objective of this concept is to design a memory efficient FFT processor with low power consumption. Enhanced memory addressing scheme is proposed to deal with these complex and higher radix FFT processors. Dual port merged bank memory is designed in-order to deal with memory based FFT processors. Each and every butterfly unit needs one memory to store those computational permutations. So, if radix of FFT increases, memory requirement increases. Implies, more density occupancy, more power consumption is yielded. Here in this concept, area efficient algorithm (Algorithm AE) with single-port, merged-bank (SPMB) memory Algorithm with Low Power (LP) using cached memory (CM) are proposed to deal with memory based FFT processor problems. The butterfly unit in this concept is implemented with multiplier and adder modules. An efficient and enhanced algorithm like Radix-16 modified booth and carry skip adders are used in this process.