Abstract

It is always being a concern since many years that data moving in networks must be secured from eavesdropping. Data encryption is considered one of the effective methods which challenge cryptanalyst to find the useful information from the encrypted data. Recently this focus has now shifted to encrypting data at rest that is encrypting data for secondary storage devices. The usefulness of this data encryption method is always a challenge for cryptographic researchers to prevent it from cryptanalyst attacks. AES-XTS is the method of encrypting data that is designed for storage devices that provides encryption based on tweak value which makes it less vulnerable for cryptanalyst attacks. This mode has been recently implemented on software as well as hardware. The FPGA provides a way to achieve the fast encryption process with sustainable throughput with a little cost. This paper presents an implementation of AES-XTS on FPGA using memory based pipelined design. After successful synthesizing, placement and routing we got the highest efficiency of the proposed design. The implementation is being incorporated by using the Digital Clock Manager (DCM) feature of FPGA with two DCMs are cascaded with the incorporation of on-the-fly key generation to achieve the time effective implementation and also an enhanced implementation of one of the AES sub-modules is incorporated. The proposed scheme is implemented on Virtex V- XC5vlx50-3ff676 FPGA.

Highlights

  • Storage encryption is considered one of the important aspects in today’s computing environment

  • Our work mainly focuses on achieving acceptable throughput for encryption of secondary storage devices

  • This section is devoted to the FPGA implementations of AES that incorporates the use of FPGA embedded memory features such as block RAM (BRAM)

Read more

Summary

Introduction

Storage encryption is considered one of the important aspects in today’s computing environment. The data encryption for storage devices that involves tweak value preserves block cipher modes of operation and is considered to be a building block for achieving ­built-i­n disk encryption [1]. Tweakable block ciphers offer several advantages as described in [2]. Software based encryption consumes more power as well as slow and not secure [4] but it is considered to be economically feasible [5], scalable, flexible and works across different hard disk platforms and types, which helps in easy management [5]. It costs less to implement than external encryption modules and consumes less power than software encryption because of dedicated, optimized hardware and better security [4]. This paper is an enhanced version of the paper published in [12]

Literature Review
Results & Discussion
AES Encryption Process
Conclusions
Full Text
Published version (Free)

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call