Abstract
Because of the increasing integration of the chip, three-dimensional integrated circuit (3-D IC) has emerged to resolve the problem, but 3-D integration is also facing more serious challenges, such as thermal stress. The thermal stress of through-silicon via (TSV) structure affects device performance and causes severe reliability problems by reducing carrier mobility. In this paper, we propose an effective method to reduce the thermal stress of TSV by means of shallow trench isolation (STI). We use Cu and silicon dioxide as materials, evaluating the thermal stresses with finite element analysis (FEA) and comparing the stresses in different situations. Finally we derive the stress data and calculate the keep-out zone (KOZ) of the different structures and find that STI can reduce the TSV thermal stress by 10.3~25.S%.
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