Abstract
The Bidirectional Network on Chip (Bi-NoC) architecture is more efficient than the conventional architecture because in conventional architecture the unidirectional flow is used where as in Bi-NoC the two way data flow can be performed. The XY routing algorithm is used to perform the architecture. The Bi-NoC architecture allows each channel to transmit in all direction and increases the bandwidth, reduces the access latency and reduces power consumption. The pipelining architecture is used in this study instead of parallel architecture because this performs the reduction in size of the architecture with better result. Also it produces better transmission in the router with reduced traffic and also has less amount of access latency which enhances the performance through better resource utilization. In this proposed method the number of flip flops reduced by 35.9% and the access latency is reduced by 18.9% when compared to existing method.
Highlights
The Network on Chip is the emerging technique in the field of Very Large Scale Integrated Circuits (VLSI)
The total number of flip flops used in the bidirectional router is 35.9% lesser than the generic router
The BiNoC architecture increases the speed in the router
Summary
The Network on Chip is the emerging technique in the field of Very Large Scale Integrated Circuits (VLSI). This NoC is used to communicate two or more IP cores in System on Chip (SoC). NoC has the better improvement over the System On chip busses and over the cross bar switches This reduces the power consumption while compared to the SoC i.e., the requirement of source power in the SoC is high and it can be reduced by the NoC architecture. By the use of NoC architecture in the field of VLSI it reduces the size of the architecture since it has reduced busses lines and transmission lines The unit such as memories, processor cores and IP blocks exchanges the data the public transportation for the traffic information
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