An Asynchronous Bundled-Data Template With Current Sensing Completion Detection Technique

Abstract

An asynchronous circuit design paradigm can address the increasing energy efficiency and speed demands of portable electronic devices. However, designing a low-cost event-driven asynchronous circuitry is a challenging task. In this brief, we propose a novel asynchronous bundled-data event-driven template created by using the current sensing completion detection (CSCD) technique. The proposed template has the advantages of the cost-efficient characteristics of bundled-data circuits without suffering the disadvantages of PVT-sensitive matching delay cells. An asynchronous RISC-V processor was designed and thoroughly compared with its synchronous counterpart and the popular RISC-V cores to validate the effectiveness of the proposed template. The asynchronous processor delivers the same performance as the synchronous counterpart while consuming only 80.09% of the power. Alternatively, the asynchronous processor achieves a 1.32x speedup under the same power consumption. In addition, the asynchronous processor leverages 1.48x-3.23x energy efficiency against the other popular RISC-V cores.