Abstract
Compared to its synchronous counterpart, asynchronous design potentially provides many advantages in terms of power consumption, execution speed, and circuit reliability. This paper presents and discusses a complete new asynchronous circuit design flow of an 8-point Fast Fourier Transform circuit, a common building block in digital signal processing applications, starting from the radix-2 8-point decimation-in-time Fast Fourier Transform algorithm development to the final asynchronous gate netlist implementation and verification. The asynchronous hardware implementation is based on Null Convention Logic design methodology, a Quasi-Delay-Insensitive asynchronous design paradigm that has accomplished important advancements in recent years. The coarse-grained Null Convention Logic based 8-point Fast Fourier Transform circuit, implemented in a built-in commercial 65 nanometers process cell library, is functionally correct compared to its synchronous equivalent and can work at the maximum frequency of 8 Megahertz.
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