An area-efficient reconfigurable binary tree architecture

Abstract

The VLSI layouts of most fault-tolerant binary tree architectures are based on the classical H-tree layout, resulting in low area utilization and an unnecessarily high manufacturing cost due to the waste of a significant portion of silicon area. An area-efficient approach to the reconfigurable binary tree architecture is presented. Area utilization and interconnection complexity of the proposed design compare favorably with other known approaches. The use of the coverage factor makes it possible to analyze the system reliability by means of the Markov model. Unlike previous reliability studies in which chips are assumed to be defect-free, this analysis considers the fact that an accepted chip may have used spares to replace manufacturing defects, and the number of spares available for tolerating operational faults may thus vary from chip to chip. The developed analytical model for reliability is readily extended to other VSLI/WIS-based multiprocessor systems. >