An area optimization of decimation filter using CSD representation for hearing aid application

Abstract

Nowadays in wireless and audio application the use of efficient digital filter is increasing because of the speed of conversion and the less hardware requirement. The hearing aid application needs an efficient methodology, fast performance, less hardware, and less power consuming digital filter. The decimation filter provides these objectives. This paper presents design and implementation of the three stage decimation filter for hearing aid application. Unlike existing decimation filters, we design the filter architecture using canonic signed digit (CSD) representation. The CSD representation is suitable for common sub expression elimination, and it significantly reduces the number of adders required for the filter synthesis. Each digital filter structure is simulated using Matlab, and its complete architecture is captured using DSP Blockset and simulink. The resulting filter architecture has high throughput, less hardware and consumes less power than the conventional filter. The proposed digital filter hardware architecture can be implemented using field-programmable gate arrays (FPGAs).