An area efficient low power Phase-Frequency Detector for PLL Applications

Abstract

This paper presents an area-efficient low power phase frequency detector (PFD) for phase-locked loop (PLL) applications in 90nm CMOS technology. PFD is a basic building block in a PLL based frequency synthesizer and is used for all modern wireless communication system to generate carrier frequency. By implementing two gate diffusion input (GDI) cells based simple PFD, chip area, power consumption, and delay is reduced compared with the conventional D flipflop based PFD. Simulated for pre-layout and post-layout design, the functioning of the model is assessed and its compatibility is dissected using the process corner analysis, temperature swept analysis, in multifarious environments. This simple structured PFD dissipates the layout area of 26.95μm2. In addition, it consumes DC power of 2.391fW. Finally, equating with the state-of-art PFD model, the implemented model has exhibited improved performance in terms of low DC power consumption, dead zone, and layout area.