An Application Specific Instruction Set Processor optimized for FFT

Abstract

This paper presents an Application Specific Instruction Set Processor (ASIP) pruned for high-throughput and variable-length Fast Fourier Transform (FFT), which is a key component of various Orthogonal Frequency Division Multiplexing (OFDM)-based wireless communication standards. The ASIP executes dedicated FFT instructions to process two radix-4 or four radix-2 butterfly operations every clock cycle. Furthermore, a shuffle-embedded register file and a programmable memory access coprocessor are employed to tackle the memory access bottleneck and reduce power consumption. The implementation results show that our ASIP requires only 892 clock cycles for a 1024-point FFT, which outperforms TI TMS320C64x DSP and Tensilica ConnX ASIP by 6.74X and 2.03X, respectively. A test chip of the proposed ASIP was fabricated using CMOS 65nm process with the core area of 1.9mm2. It consumes 85mW when it runs at the maximum frequency of 150MHz.