An anti-aliasing filter for ΣΔ ADC

Abstract

An anti-aliasing filter for ΣΔ ADCs using a combination of active RC and analog FIR filters is presented in this letter. The first order active RC filter is set at 100kHz to minimize the die size and variations of linear phase and gain in 0–4kHz passband. The 2-tap FIR filter provides more than −53dB attenuation at 2MHz ±4kHz frequency range. The proposed filter achieved more than −76dB attenuation at sampling frequency with ±0.01° phase linearity and ±0.02dB gain variation within 0–4kHz bandwidth. The active die area of the fully differential filter is 0.17mm2 in 0.5µm CMOS technology. The experimental and simulation results have been obtained and the feasibility of the proposed method is shown.