An analytical model of the surface-potential-based source-pocket-doped cylindrical-gate tunnel FET with a work-function-modulated metal gate

Abstract

A new surface-potential-based analytical model for a source-pocket-doped cylindrical-gate tunnel field-effect transistor (FET) with a work-function-modulated metal gate is proposed herein. The inclusion of a highly doped source pocket layer improves the drain current by two decades because of the higher band-to-band tunneling probability of charge carriers in the vicinity of the tunneling junction. Also, the presence of the work-function-modulated cylindrical gate reduces the subthreshold swing (SS) further below 60 mV/decade and thus enhances the $$I_{60}$$ performance. The potential distribution of the model is determined using the two-dimensional (2D) Poisson equation with appropriate boundary conditions and plays a significant role in the calculation of the shortest tunneling distance and the drain current. The position and width of the pocket layer in the source region are optimized with the aim of achieving the maximum current switching ratio (ION/IOFF) and $$I_{60}$$ and least possible subthreshold swing. Due to its high current switching ratio, significantly improved $$I_{60}$$, and remarkably low SS characteristics, the proposed model represents one of the probable devices to replace complementary metal–oxide–semiconductor (CMOS) technology. The results of the analytical model are validated against those obtained using the Synopsys technology computer-aided design (TCAD) device simulator.