Abstract
An analytical model for the above-threshold characteristics of long-channel, small-grain and thin channel polysilicon thin film transistors (TFT's) is presented. This model is constructed by considering the barrier potential and the carrier trapping effect at grain boundaries of the channel. A band tail state located at E/sub c/-0.15 eV is taken into account to simulate the I-V characteristics. Based on the model, the theoretically simulated results show good agreement with experimental data of plasma-passivated and unpassivated TFT devices in a wide range of gate and drain biases and temperature. The correlation of transconductance to gate bias is also investigated. It is found that the decrease of grain-boundary barrier potential with gate voltage enhances the transconductance, while this enhancement effect becomes insignificant and causes a decrease of transconductance at high gate bias. >
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