An analysis of the operation and SET robustness of a CMOS pulse stretching circuit

Abstract

The cascaded asymmetrically sized inverters can be employed as pulse stretchers, for the measurement of very short single event transient (SET) pulse widths (< 200 ps). This paper analyzes, through the circuit simulations, the effects of various design and operating parameters on the normal operation and SET robustness of a two-inverter pulse stretcher designed in 250 nm bulk CMOS technology. It was shown that the SET hardness of the pulse stretcher can be enhanced by upsizing all transistors in the pulse stretcher without changing the sizing ratio. The SET hardness can also be improved by upsizing the load, but this approach is less effective than the pulse stretcher upsizing. Both upsizing approaches have a negligible impact on the normal operation of the stretcher, i.e. output pulse width. In addition, the operation and SET robustness of the pulse stretcher can be influenced by the operating temperature and supply voltage variations, and these effects should be considered in the design process. Based on the acquired simulation results, a general approach for the design of a radiation hardened CMOS pulse stretcher has been proposed.