An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability

Abstract

In this paper, an analog enhanced all digital fractional-N PLL is proposed. An analog feed-forward circuits replace the time-to-digital converter used in conventional all digital PLL (ADPLLs) to provide a linear phase modulation path which is insensitive to quantization error and non-linearity of digital controlled oscillator (DCO). Its advantages include 1) Eliminating fractional spurs and noise induced by quantization error and the latency induced by the digital circuits in ADPLLs 2) Relaxing both digital controlled oscillator (DCO) and analog feed-forward circuit design requirements. 3) Providing a linear phase modulation path which can be self calibrated by using the digital loop filter. 4) Reducing loop filter area by using digital loop filter. The fractional spurs are 9 to 30 dB lower than the latest reported ADPLLs. At 3.6 GHz under fractional-N mode operation, the fractional spur is under -75 dBc, the phase noise is -115.6 dBc/Hz @400 KHz, -134.9 dBc/Hz @3 MHz. The performance satisfies GSM/GPRS/EDGE system requirements.