An analog circuit synthesis tool based on efficient and reliable yield estimation

Abstract

Analog circuit design has become a very challenging and time consuming process for circuit designers due to increased non-idealities and worsening variability phenomena. In order to facilitate the design process, several analog circuit sizing tools have been proposed in the literature. These tools have then led to yield-aware ones, where a certain yield is targeted. However, the type of variability analysis to be employed is still a topic of discussion due to the challenging trade-off between accuracy and efficiency of the yield analysis. Quasi-Monte Carlo (QMC) approach is one of the efficient techniques that provides efficient variability analysis via deterministic, and more importantly homogeneous sampling. The major bottleneck of the conventional QMC is that there is no practical way to calculate the estimation error. Scrambled-QMC has been utilized to obtain the error bounds of the estimation, thanks to multiple runs of randomized sample sets. However, the requirement of multiple runs substantially increases the synthesis time. To overcome this problem, this paper proposes a novel yield-aware analog circuit sizing tool, where an adaptive sample sizing algorithm for scrambled-QMC is employed in the yield estimation part.