Abstract
An analog integrated front-end circuit for the RDS (Radio-Data-System) digital decoder is described. The core of the circuit is an 8th-order switched-capacitor (SC) bandpass filter at 57 kHz with linear-phase response in a 3 kHz bandwidth. A low-offset comparator provides the squared signal for the digital decoder. Antialiasing and smoothing filters are also included in the chip, as well as the clock generation for the SC section; few external components are required. Integrated in a high-performance BiCMOS technology, the circuit operates from a single 5-V supply and dissipates 45 mW. The die size is 5 mm/sup 2/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call