An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation

Abstract

An all-digital spread spectrum clock generator (SSCG) using two-point modulation is presented. To calibrate the gain mismatch between two modulation paths, a background gain calibration method is proposed. To reduce power consumption and design complexity, the bang-bang phase-frequency detector (BBPFD) is used instead of the time-to-digital converter (TDC). The prototype chip has been fabricated in a 65-nm CMOS process and it consumes 6 mW at 2.5 GHz. The measured minimum rms jitter is 1.58 ps.