An algorithm for improving partitions of pin-limited multi-chip systems

Abstract

We present a method for improving a topological partition of a logic circuit. Circuits are partitioned so that they may be amplemented by a number of modules (for example, by a number of chips). By reducing the number of i/o pins necessary for communication between the modules we reduce the size of the chips needed to implement the modules, and thereby may also reduce the number of chips needed to implement the modules. Interpartition communication is organized into many unidirectiona/ channels connecting the blocks. The number of lines necessary JOT implementing a communication channel is reduced by minimizing the amount of information that the channel must transmit, and by encoding the information that is transmitted. The reduction in the channel size usually is accompanied by an increase in the amount of logic in the partition modules. Thus this method is most effectively applied to design styles that are pin-limited; .i.e design styles that have a high ratio of logic area to number of input/output ports. We apply this method to a number of example communication channels and show large reductions in the size of the channels. We also show examples of designs that have fewer chips, OT designs have smaller chips after application of these methods.