Abstract
An agile fractional-N PLL frequency synthesizer is implemented in 0.35/spl mu/m CMOS technology. A generic transceiver architecture is proposed for 2.5G GSM applications. The synthesizer uses a 26MHz reference frequency, and has 70 KHz loop bandwidth. The synthesizer chip provides agile switching with a settling time of 160 /spl mu/s for 35MHz frequency step, low in-band noise with 0.5/sup 0/-RMS phase error and fine frequency resolution of less than 50Hz using a new /spl Sigma//spl Delta/ modulator with a dual transfer functions. The synthesizer layout is 1.5 /spl times/ 1.4 mm/sup 2/. The digital part of the synthesizer operates at 1.5V-supply, while a 3-V supply is used for the analog blocks.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
