Algorithmic ΔΣ-modulated FIR filter

Abstract

We present an algorithmic /spl Delta//spl Sigma/-modulated FIR filter which computes digital convolution of a continuous-time analog input signal with a programmable digital impulse response. Selective sampling of the input signal controlled by unary-encoded FIR coefficients yields bit-serial analog-digital multiplication. A /spl Delta//spl Sigma/-modulated analog-to-digital converter samples a time-varying input at multiple instances in time generating a quantized version of the average of all weighted samples. Computational throughput of an arbitrary FIR filter is maximized by algorithmic resampling of the modulation residue to obtain higher resolution bits. This yields a bit resolution linear in the number of conversion cycles. A 1.9mm /spl times/ 1.3mm 128-channel FIR filter integrated prototype was fabricated in a 0.35 /spl mu/m CMOS technology. It yields a computational throughput of up to 3.8 GMACS, with computational quantization time, power dissipation, and integration area comparable to those in a conventional oversampling analog-to-digital converter.