Abstract
The communication architecture in a distributed memory multi-processor system must provide reliable and flexible communications with minimal latency to fully utilize the performance advantage offered by the inherent parallelism. An inefficiently designed architecture introduces ‘hot spots’ in the inter-processor communications and degrades the potential speed-up possible. This paper compares existing switching strategies on multi-processor systems and describes the development of an adaptive switching architecture for a circuit-switched multi- processor system with an arbitrary interconnection topology. The switching architecture employs dynamic reconfiguration of the communications path to provide highly efficient and fault-tolerant inter-processor communications.
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