Effect of the interprocessor communication mechanism on performance of a parallel processor system

Abstract

The effect of the interprocessor communication (IPC) mechanism on system performance in a multiple-instruction-stream-multiple-data-stream (MIMD) parallel-processor system is investigated. The architecture and a high-level implementation are specified for a parallel-processor system which uses multiple horizontal and vertical buses to interconnect processing elements. A software simulator is developed to support evaluation of systems based on the architecture, and experiments are conducted with the simulator to evaluate system performance. As a basis for comparison simulations are also conducted for the architecture and implementation of a single-bus parallel-processor system derived from the horizontal/vertical-bus system. The experiments deal with the parallel solution of a five-body problem; system performance is measured as processor speed, and IPC mechanism speeds are varied independently over a wide range. The results demonstrate the significant effects on performance of both the problem partition and the relative speeds of the processors and the IPC mechanism; they also demonstrate the extent to which the multiple-bus architecture provides higher performance than the single-bus architecture in this application. >