An Adaptive Body-Bias Generator for Low Voltage CMOS VLSI Circuits

Abstract

A CMOS body-bias generating circuit has been designed for generating adaptive body-biases for MOSFETs in CMOS circuits for low voltage operation. The circuit compares the frequency of an internal ring oscillator with an external reference clock. When the reference clock is “high,” forward body-bias is generated. When the reference clock is “low,” a reverse body-bias is generated. The forward body bias is limited to no more than 0.4 V to avoid CMOS latchup. The reverse body bias is limited to 0.4 V and is very effective in suppressing the subthreshold current. The frequency adaptive body-bias generator circuit has been implemented in standard 1.5 μm n-well CMOS technology and simulated using SPICE. Excellent agreement is obtained between the simulated output characteristics and the corresponding experimentally measured behavior. It is also demonstrated that up to 90% leakage current in CMOS circuits can be reduced by applying the adaptive bias generator to lower threshold voltage CMOS circuits. The design is simple and can be embedded in low power CMOS designs such as the physical nodes of wireless sensor networks.