An active learning/teamwork approach to implementing an integrated circuit design cycle in an advanced hardware description language course

Abstract

The design of digital application specific integrated circuits (ASICs) has recently shifted from schematic entry toward the use of hardware description languages such as VHDL or Verilog. Powerful design tools are required to perform the design synthesis, simulation and verification of these chips prior to fabrication. Most courses in VHDL or Verilog focus on the details of the language rather than the process and techniques required by industry in creating an actual chip. This paper describes an approach currently being used for an advanced VHDL course which attempts to have students learn not only the hardware description language, but also the design tools and process required to produce an actual working ASIC. In addition to discussing the learning techniques used, this paper also describes handling issues such as uneven contribution efforts and individual assessment.