An 8-bit Compact Architecture of Lesamnta-LW Hash Function for Constrained Devices

Abstract

A very compact architecture for the lightweight 256-bit hash function Lesamnta-LW is presented in this paper. The proposed architecture has an 8-bit datapath and requires very few hardware resources and, therefore, can be a prime candidate for resource constrained devices. The proposed architecture was designed and implemented on the BASYS3 board (Artix 7 XC7A35T) using the VERILOG hardware description language. The implementation utilizes only 434 FPGA LUTs, 474 FFs and reaches a throughput equal to 50 Mbps at 161 MHz clock frequency.