Performance Analysis of Secure Hash Algorithm-2 (SHA-) and Implementing on FPGA

Abstract

AbstractIn this modern and clumpsy world, security is more important than everything. Today, security of system is one of the fastest growing field in the world. With the goal of reduction in the accumulating area, throughput and power of the hardware performance of a crypto-analyzed system, secured hash functions of hardware working are extremely efficient and great importance. Now for most of the security services, hash function algorithm has become the default choice. SHA-2 (Secure Hashing Algorithm-2) hash family is a new security algorithm which is widely used in modern computer systems. Sometimes SHA-1 Hashing algorithm produce same hash for different files which is also known as a collision, as the number of hash functions increases, the smaller the number of chances that the standards will create the same hash function, and hence, SHA-2 algorithm is always being used in numerous cryptographic algorithms. Confidentiality, integrity, and authenticity are the major application areas of cryptography. The use of FPGA has vital advantages for implementation of cryptographic algorithms. The proposed work implements SHA-2 algorithm on cryptographic processor for efficient performance of cryptosystem using Verilog hardware description language (HDL).KeywordsSecurityConfidentialityIntegrityAuthenticitySHA-1SHA-2