An 8-bit 900MS/S two-step SAR ADC

Abstract

Several hundreds of MS/s to 1GS/s 8-bit low-power ADCs are demanded in various portable applications. Conventional successive-approximation register (SAR) architecture has the benefits of energy efficiency and small area but it suffers from low conversion rate. Recently, multi-bit per cycle SAR [1], multi-comparator SAR [2], pipeline-SAR, and time-interleaved SAR architectures [3] are reported to improve the conversion rate. In this work, an asynchronous two-step single-channel SAR ADC using a charge sharing technique and a self-triggered-latch (STL) technique is proposed to accelerate the conversion rate and reduce the power consumption. This ADC achieves 44.3dB SNDR and 19.1 fJ/c.-s. at 900MS/s with an active core area of 0.0049 mm2 in 40nm CMOS process.