A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs

Abstract

Novel self-timing switch-driving registers for high-speed successive approximation register (SAR) ADC is proposed. This circuit can provide fast charging path from comparator output to DAC array of SAR ADC and store the comparison results simultaneously at each approximation bit-cycle. The propagation delay from input to output of the register is about 60 ps only in a 90 nm CMOS process. By using this technique, the 5-bit SAR ADC achieves 30.3 dB SNDR with 285 MS/s high sampling-rate, power consumption is 10.5 mW.