Abstract
An 8-bit, 3.2 GS/s, time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) with a non-buffered hierarchical demultiplexing architecture is proposed and fabricated. Compared to a typical hierarchical TI-ADC, (i) all track-and-hold (T&H) related noise sources and (ii) wide-band amplifiers for buffering of the input signal are avoided. In this way, the proposed solution can improve the signal-to-noise-ratio and reduce power consumption. The concept is demonstrated in an 8-bit 3.2 GS/s TI-ADC design based on 32 asynchronous SAR ADCs and fabricated in a 0.13μm CMOS process. The prototype includes (i) a programmable delay cell array to adjust four front sampling phases, and (ii) a 25.6 Gb/s low voltage differential signaling (LVDS) interface. Measurements of the fabricated TI-ADC show 44.6 dB of peak signal-to-noise-and-distortion ratio and 105 mW of power consumption at 1.2 V.
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