A 4GS/s 8-bit SAR ADC with an Energy-Efficient Time-Interleaved Architecture in 130nm CMOS

Abstract

The design, implementation and characterization of an 8-bit, 4 GS/s, time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) with a non-buffered hierarchical demultiplexing sampling architecture are presented in this work. The core of the ADC is composed of an arrangement of 32 asynchronous SAR ADCs ranked in a $4\times 8$ hierarchy. The proposed fully dynamic SAR ADC features a noise-configurable comparator, configurable asynchronous clock and background DC offset calibration. The non-buffered input signal circuit includes an input matching network for tracking bandwidth enhancement. The design also has a programmable delay cell to adjust the clock sampling phases mismatch, and a 32 Gb/s low-voltage differential signaling (LVDS) interface. The prototype is fabricated in a $0.13 \mu \mathrm{m}$ CMOS process. The TI-ADC achieves 7.09 bit of peak ENOB, 1.3 GHz input bandwidth and 93 mW of power consumption at 1.2 V.