An 88.9-dB SNR Fully-Dynamic Noise-Shaping SAR Capacitance-to-Digital Converter

Abstract

This article presents an energy-efficient noise-shaping successive-approximation register (SAR) capacitance-to-digital converter (CDC) for high-resolution capacitive sensor applications. Based on a 12-bit SAR architecture, quantization noise is shaped by the first-order FIR-IIR loop filter. The proposed loop filter comprises dynamic amplifiers (DAs), and it is designed to be insensitive to DA gains’ variations. Under process, voltage, and temperature (PVT) variations, the loop filter is stable and retains in-band noise suppression ability without the gain calibration. The CDC is implemented in a differential configuration for a single-sensor measurement with an energy-efficient capacitive digital-to-analog converter (CDAC) switching method. It does not require any replica or dual capacitor sensor for differential operation. In the proposed CDC, a dynamic comparator with a common-mode (CM) rejection is proposed to compensate for the instability because the parasitic capacitance causes CM voltage deviation of the CDAC and loop instability. The proposed CDC is fabricated in a 180-nm CMOS technology with an active area of 0.25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It dissipates 63.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> at a sampling frequency of 320 kHz. Given that all circuits operate dynamically, the sampling frequency is scalable from 3.2 to 320 kHz. The prototype CDC achieves an 88.9-dB signal-to-noise ratio (SNR) and a figure-of-merit of 139 fJ/conversion-step.