Abstract
A power-efficient continuous-time delta-sigma modulator (CTDSM) employing a single-amplifier biquad (SAB) based topology is proposed. The modulator incorporates a proposed twin-T SAB topology where the excess loop delay (ELD) is compensated by injecting a feedback signal into an internal node of the SAB while cooperating with an additional phase-compensation resistor. A low-power time-to-digital converter (TDC) with an embedded data weighted averaging (DWA) function is proposed as the quantizer, which mitigates the mismatch issue in the feedback DACs. Fabricated in 90nm CMOS, the proposed CTDSM achieves peak SNDR of 67.2dB over an 8.5MHz signal bandwidth, while consuming 4.3mW at 300MHz sampling frequency, and scores a FoM of 135fJ/conv.-step.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
