An 80% larger-current-output negative CMOS charge pump with 10% area penalty for sub-1-V-VCC negative-word-line DRAMs

Abstract

Abstract A new CMOS negative charge pump scheme is proposed in this paper. This new pump scheme can generate output current which is 80% larger than the conventional pump with the sacrificial 10% area penalty. This new pump is regarded to be suitable to sub-1-V-VCC DRAMs with the negative-word-line (NWL) scheme, where the dynamic current consumption is expected to be very large.