An 8-ns 256K ECL SRAM with CMOS memory array and battery backup capability

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The authors describe the first high-performance, high-density ECL SRAM (emitter-coupled-logic static random-access memory) compatible with battery backup techniques. The 256K device has a measured access time of 8 ns. Fabricated in a 0.8- mu m BiCMOS process, the chip uses 117- mu m/sup 2/, full-CMOS, six-transistor memory cells and measures 6.5*8.15 mm/sup 2/. The design methodology described here illustrates the extent to which bipolar devices can be integrated into the periphery of a CMOS memory array. This integration was achieved through the use of a novel sensing scheme which provided three stages of bipolar differential sensing, with the first stage of sensing taking place directly on the bit lines. >