Abstract
We propose a new approach in reducing the power consumption of the successive approximation register Analog to Digital Converter (SAR-ADC) by changing the convergence algorithm of the Digital to Analog converter (DAC) input of the SAR-ADC. Different search algorithms such as binary search tree, moving binary search tree (BST), least significant bit shifter (LSB), adaptive algorithm and split-register moving BST algorithm are designed and analyzed for faster convergence of the DAC input. In this paper, we design a 0.8 GS/s, 8 bit (Effective number of bits (ENOB)—7.42), 8.352 mW SAR ADC with a proposed moving BST algorithm in 65 nm CMOS which ranks amongst the current state of the art ADCs with a FOM 65.25 fJ/step.
Highlights
Analog to digital converters (ADC) are among the most important electronic structures due to the technological shift and advances in digital electronics
There are many tradeoffs in designing ADCs including power, cost, sampling speed, resolution; the most challenges are in designing a high frequency and low power ADC
The pioneers in designing ADC have considered remodeling the different state of the art components like the comparator, S/H circuit and Digital to Analog converter (DAC) (Figure 1) to reduce the power consumption
Summary
Analog to digital converters (ADC) are among the most important electronic structures due to the technological shift and advances in digital electronics. Successive approximation register (SAR) analog-to digital converters (ADCs) require several comparison cycles to complete one conversion, and have limited operational speed [1] [2]. The pioneers in designing ADC have considered remodeling the different state of the art components like the comparator, S/H circuit and DAC (Figure 1) to reduce the power consumption. We propose different search algorithms for SAR-ADC and analyze the design and performance tradeoffs We feel that this could potentially be used to design low power consumption ADCs. Most commonly [4], binary search algorithm is used for DAC input convergence since it is fastest search algorithm existing for finding a value in a random group of arranged numbers with O (logn) as its Big O notation. In all our cases in this paper, we are assuming the number of bits to be 10 (0 to 1023) for explaining the proof of concept
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