Abstract
Traditional single-slope analog-to-digital converter (SS ADC) faces a speed limitation that constrains the exposure speed of CMOS image sensors (CIS). To enhance the conversion speed of SS ADCs used in high frame rate CIS, a two-step column-shared ADC based on Flash/SS architecture is proposed. The ADC design approach is based on the concepts of time compression and multi-column sharing. On one hand, a Flash ADC and differential ramps are introduced while two comparators are multiplexed to enhance the conversion speed. On the other hand, a multi-column shared design is employed in some circuits to reduce the average area and power consumption per column. Under a design environment of 256 × 256 pixel resolution, the simulation results show that the row time of ADC is 5.4μs, the column-level average power consumption is 129.5 μW, and the FoMa is 527 fJ/step. Compared to the conventional 11-bit two-step SS ADC, the proposed ADC not only optimizes quantization speed but also simplifies the redundant calibration structure.
Published Version
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