An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS

Abstract

A pipelined successive approximation register (SAR) analog-to-digital converter (ADC) that partially reuses the dynamic comparator as PVT stabilized residue amplifier is presented. Rather than reusing the entire comparator structure which experiences exponential gain characteristic related to time, thereby being sensitive to PVT variations, the comparator is configured as gain-boosted dynamic amplifier during amplification. By using an auxiliary single pole amplifier to track the PVT variations, the amplifier can achieve stable gain. By realizing the auxiliary amplifier also in dynamic manner, the presented full dynamic ADC ensures a good energy efficiency. The prototype ADC fabricated in 65 nm CMOS process achieves 2.12 mW total power consumption at a 1.2 V supply with a signal-to-noise distortion ratio of 60.7 dB and a spurious-free dynamic range of 70.5 dB for a near Nyquist input.