An 0.18 μm embedded FCRAM ASIC with DRAM density and SRAM performance

Abstract

A large scale embedded Fast Cycle RAM, FCRAM, macrocell for ASIC applications is described. It has 3.52 Giga Byte Per Second data throughput using 512 bit internal data bus, even in cases when the access is completely random. The macrocell is generated from a compiler, while the memory capacity and the data bit width can have 72 variations. Furthermore, a larger variety of memory and data bus types as well as performances are obtained by arranging multi-bank organizations using multiple macros on a chip. Cost/performance of the embedded FCRAM is a better solution to SRAM or conventional DRAM approaches. Data communication ASICs like: classification engines, routing protocol controllers, traffic managers, switching processors, can benefit from the higher density and higher random cycle performance offered by FCRAM when compared to SRAM or traditional DRAM.