A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-Memory

Abstract

This paper describes an approach to a low power and high speed data transfer scheme in the internal data bus of an AS-Memory which has ASIC circuitry and memory array. Pulse width modulation, which is operated asynchronously, is applied to the wide internal data bus. An automatic gain controlled amplifier which amplifies many small signals from the memory array is also newly developed to achieve a fast data output. Applying this architecture to an AS-Memory, the area and power consumption of the internal data bus interface can be reduced to 25% and 36%, respectively.