Abstract
The MACH (macro array CMOS high performance) family of programmable logic devices (PLDs) is described. Combining an innovative and optimized silicon architecture with an advanced 0.8 mu m double-metal, electrically erasable CMOS technology, the MACH family offers the speed of low-end programmable array logic (PAL) devices (15 ns propagation delays), with the density of field programmable gate arrays (900 to 3600 equivalent gate densities), providing 3 to 12 times the functionality of existing PLD solutions. >
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