Alternative USJ formation and characterization methods for 45 nm node technology

Abstract

Several alternative methods of forming and characterizing ultra-shallow junctions for the 45nm node (Xj=9.5nm) to extend planar single gate CMOS for bulk or SOI technologies are being investigated. To continue gate length scaling (Lg) and optimize gate overlap control, the industry will move from Spike/RTA annealing at the 65nm node to diffusion-less activation using high temperature milli-second annealing (Flash/RTA or non-melt laser), low temperature SPE or their combinations to optimize Rs and Xj. This is driving the development of new high dose/low energy implanter designs with: (1) high tilt angle capabilities for gate over lap control, (2) uniform beam parallelism across 300mm wafers to eliminate asymmetrical transistor effects and (3) high productivity at 200eV boron equivalent energies with no energy contamination using new molecular dopant species (B10H14 and B18H22). If these techniques are unsuccessful in achieving the 45nm node shallow p+ junctions with improved Rs dopant activation above Bss with acceptable junction leakage and device channel mobility enhancement then alternative non-implantation doping methods will be introduced such as in situ doped SEG and infusion DCD. Also, accurate characterization of these shallow junctions is critical so new non-penetrating 4PP Rs measurement techniques are being developed along with new spreading resistance depth profile analysis to determine the electrically active dopant profile as opposed to the SIMS chemical dopant profile.