Alternative memristor-based interconnect topologies for fast adaptive synchronization of chaotic circuits

Abstract

Resistive switching devices (memristors) constitute an emerging device technology promising for a variety of applications that are currently being studied. In this context, the use of memristors as coupling elements of the dynamics of chaotic circuits for adaptive synchronization purposes, was recently proposed and the passive crossbar array was evaluated as target interconnect medium. Nonetheless, memristors may suffer from defects and degradation. Therefore, this work evaluates the impact of memristor switching faults in an adaptive chaotic synchronization scheme, exploring at the same time the fault-tolerance of the crossbar architecture. Moreover, inspired from our observations in the stuck-at-OFF fault analysis of the memristive crossbar, some alternative scalable memristive interconnect patterns are suggested, whose performance is found independent of the number of interconnected chaotic circuits, requiring a much smaller number of total memristors than the crossbar array. All simulations are based on an accurate physics-based model of a bipolar memristor with filamentary switching mechanism. Based on our results, using the alternative topologies instead of the crossbar array leads to significant savings in the synchronization time that increase with the number of interconnected chaotic units, at the cost of more limited scaling capability and fault-tolerance.