Alternate resolution strategy in multistage interconnection networks

Abstract

Multistage interconnection networks have been proposed by many research groups to provide communication between processor and memory module in multiprocessor systems. However, two different processor requests may result in a conflict on the path establishment. For multistage interconnection networks operated in circuit switching mode, the drop approach and the hold approach are often employed to solve the conflict problem in path establishment. In this paper, we propose another resolution, the preemptive hold approach, to solve the conflict problem in path establishment. The proposed approach requires a minor modification in the design of the switching element in multistage interconnection networks. From simulation results, we find that the bandwidth of our proposed resolution approach is higher than those of the other two approaches. Meanwhile, we also propose an analytical model to analyze the bandwidth of the drop approach in multistage interconnection networks.