Abstract
Interfaces between a poly(3-hexylthiophene) [P3HT] and an end-grafted (brush) layer of poly(methyl methacrylate) [PMMA] are shown using neutron reflectometry to be dependent on heat treatment. Annealing the samples allows part of the brush layer to cross into the P3HT layer creating a very asymmetric interface. We suggest that the P3HT rearrangement occurs, creating space for movement of the brush into the film. This interpenetration was observed with two different molecular weight (17.5 and 28 kg mol−1) P3HT films. Output characteristics of devices made from P3HT layers on PMMA brushes show that different amounts of heat treatment do not significantly change the device performance. Saturated hole mobilities are dependent on heat treatment, with devices made from a smaller molecular weight P3HT (22 kg mol−1) demonstrating larger mobilities than devices created using 48 kg mol−1 P3HT, but only after heat treatment.
Highlights
All-polymer eld-effect transistors (FETs) have been developed for a number of years due to their impressive processability and to further improve development of exible devices
In our earlier work,[7] we demonstrated the use of atom transfer radical polymerization (ATRP) as a means to grow poly(methyl methacrylate) (PMMA) gate dielectric layers from a gold surface
The gra ing density was kept constant, and would be expected to be of the order of 0.5 brushes per nm[2] in comparison with similar systems.[12,13] (Direct measurement of gra ing density is unreliable, but an accurate knowledge of gra ing density is unimportant in the present study.) We present data for different annealing treatments for these brushes, at temperatures above and below the glass transition of PMMA
Summary
All-polymer eld-effect transistors (FETs) have been developed for a number of years due to their impressive processability and to further improve development of exible devices. Optimal transistor performance requires layers with complete integrity as well as interfaces free of traps. This is true in the case of the dielectric layer, because leakage and short-circuiting are caused by imperfections and pinhole defects. Making thicker dielectric layers is more likely to provide layer integrity, longer channel lengths, L are required, since Lmin f t3, where t3 is the thickness of the gate dielectric and Lmin is the minimum channel length appropriate for that dielectric thickness. It is important to have the gate layer as thin as possible in order that a smaller gate voltage be required to maintain the required charge density at the interface.[5,6]
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
