All-Digital Clock Calibration for Source-Synchronous High-Speed I/O Links Based on Phase-to-Digital Conversion

Abstract

Wire-linked high-speed interfaces play an important role in modern computing systems. They are required to transfer enormous amounts of data in a short time between processors, memories and periphery. Many efforts are put into the development of I/O links with higher data rates and lower power consumption in order to keep up with the increasing processing speed of CPUs and GPUs. Especially memory interfaces are struggling to reach the bandwidth required by the processors. Source-synchronous parallel I/O links that connect the processor and the memory with PCB interconnects are limited by the high-frequency characteristics of the PCB and the maximum number of parallel data links. New interface types with shorter interconnects and more parallelization based on a silicon interposer instead of a PCB have been introduced to tackle this problem, but due to the higher manufacturing cost these interfaces still haven’t fully replaced traditional PCB based memory interfaces. A common challenge in all parallel high-speed I/O links is the calibration of the ideal sampling time for each individual data link. The conventional method requires time consuming bit error rate measurements over a 180 ◦ wide range of possible sampling phase positions and is prone to timing center errors due to the nonlinearity of the phase generation. In this work a fast timing center calibration based on a phase measurement between the received signal and the internal clock is presented which reduces the calibration time significantly and minimizes the timing center error by compensating the nonlinearity of the phase generation. The phase measurement is performed by a fully synthesized phase-to-digital converter (PDC) offering precise phase and duty-cycle measurements of high-frequency clock signals with low power consumption. A calculation method for estimating the deviation of the PDC measurement result from the actual value due to clock jitter allows to predict the behavior of the PDC and can be used to generate jitter specifications for the clock signals. The proposed PDC also offers new possibilities in the implementation of other high-frequency clock calibration circuits such as delay-locked loops and duty-cycle correctors. Three ASICs in a 65nm CMOS process have been designed that demonstrate the feasibility in four different clock calibration scenarios of a prototype bidirectional asymmetric source-synchronous I/O link similar to the GDDR5 standard for GPU memories. The application of the PDC as a linear phase detector in delay-locked loops simplifies the design procedure and results in a small and power efficient circuit that scales well with technology thanks to the all-digital implementation. The capability of the PDC to measure the duty-cycle of high-frequency clock signals with high precision is used to correct the duty-cycle in the high-speed transceivers at different nodes with a low area overhead. In addition to the timing center calibration a voltage threshold calibration based on the duty-cycle measurement of a received clock pattern is proposed that further reduces the calibration time of single-ended I/O links and simplifies the calibration procedure.