Abstract

AbstractThe increased complexity of current generations of MEMS devices imposes new requirements for wafer bonding. Among these can be mentioned low process temperature (<400°C), precise optical alignment of substrates, ability to bond a large variety of substrates and the possibility to bond with defined intermediate layers. An important aspect in aligned wafer bonding is that alignment accuracy needs to be correlated to the type of bond process. Especially in case of processes using bonding layers the post-bond alignment accuracy will be given by the behavior of the bonding layers. This paper aims to review the main criteria to be considered in defining aligned wafer bonding processes. Particularly bonding of substrates containing electronics (e.g. CMOS wafers) is currently of high technological interest.

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