Algorithms for rare event analysis in nano-CMOS circuits using statistical blockade

Abstract

Accurate and fast characterization of the process variations of nano-CMOS circuits is becoming increasingly important for design for manufacturing (DFM) with highest yield. One of the ways to understand the circuit behavior under the process variations is to analyze the rare events that may happen due to such process variations. The Statistical Blockade (SB) is a approach for such rare events analysis. In SB, the classification threshold selection becomes very important for different tail regions which is related to the number of rare events simulation. This paper presents the values of classification threshold for different tail regions of typical circuits. It is shown that a given classifier requires different number of training samples depending on classification thresholds.