Aging Mitigation in FPGAs Considering Delay, Power, and Temperature

Abstract

Field programmable gate array (FPGA) devices are highly susceptible to transistor aging, mainly through the bias temperature instability (BTI) phenomenon. BTI can be modeled as threshold voltage increase in MOSFET transistors, which leads to the degradation in device performance. As technology scales, leakage power has turned into a major portion of FPGA total power consumption. In this paper, we study the mutual effects of BTI and leakage power by considering the temperature changes in the basic components of FPGAs. Our analysis shows that while the leakage-power reduction caused by BTI may be considered desirable, a bit-flipping scheme should still be employed to mitigate device degradation. We present an optimization problem to optimize the device performance over the device's lifetime. A postrouting aging-aware timing analysis method is also proposed to find the best flipping frequency. The simulation results show that bit flipping at a proper frequency may reduce the power consumption of device by about 5% while keeping the critical path delay below a given constraint.