Advancing Science and Technology of High-k Dielectric at ECS

Abstract

Historically SiO2 was the main driver as the transistor gate dielectric in CMOS technology. Once the thickness of SiO2 reached the onset of direct tunneling region (<1.5 nm) HfO2 -based high-k insulators were introduced to suppress the direct-tunneling leakage current. ECS started a symposium on Physics and Technology of High-k Gate Dielectrics in 2002 describing the evolution of dielectric science in nanoelectronics. In recent years transistor has transformed from a planar device to a three-dimensional device to a gate all around device. The electrical performance in these devices depends on the dielectric deposition process, precise selection of deposition parameters, pre-deposition surface treatments and subsequent thermal budget. By considering the interface reaction kinetics and thermal budget various atomic layer deposition (ALD) schemes were identified to get a stable dielectric with a robust interface. The deposition of Hf1-xZrxO2 on both silicon and germanium, a higher mobility channel material, were discussed. By doping HfO2 with ZrO2 and modifying the structural phase provides higher dielectric constant than the standard amorphous or monoclinic phase. Some of the reliability challenges of these dialectics based on dielectric-semiconductor interface were addressed and resolved. Several applications of high-k dielectrics have emerged including ferroelectric FETs and resistive random-access memory (ReRAM) devices that are being investigated for possible implementation of artificial intelligence hardware. Dr. Dolf Landheer presented his paper in the 1st symposium and from 2nd symposium onwards he was an organizer. He contributed significantly toward the advancing science and technology of high-k dielectrics and its dissemination for a long time in addition to other areas.